1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus that controls MIS (Metal Insulated Semiconductor) transistor threshold voltage, and particularly relates to a semiconductor integrated circuit apparatus capable of controlling substrate voltage of fine-detailed MIS transistors operating at low power supply voltages.
2. Description of the Related Art
In recent years, methods of lowering power supply voltage are well-known as important methods for making semiconductor integrated circuits low in power consumption. However, by lowering the power supply voltage, fluctuations in threshold voltages of MIS transistors or MOS (Metal Oxide Semiconductor) transistors have a substantial influence on operating speed of semiconductor integrated circuits.
With regards to this problem, in the related art, circuit technology for making variations in threshold voltage small has been developed. For example, as shown in FIG. 12, the following operation is carried out using a leakage current detection circuit where a stabilizing potential generated by two NchMOS transistors M1n and M2n operating in a sub-threshold region is applied to a gate of NchMOS transistor MLn for leakage current detection use and a constant current source is connected to a drain of the transistor MLn, and a substrate bias circuit. First, when the threshold voltage is lower than a target value, leakage current increases to more than a target value and the detected leakage current therefore becomes larger than a set value. As a result, the substrate bias circuit operates, the substrate bias becomes deeper, and the threshold voltage is corrected to be higher. Conversely, when the threshold voltage is higher than a target value, leakage current falls to less than a target value and the detected leakage current therefore becomes smaller than a set value. As a result, the substrate bias circuit makes the substrate bias shallower, and the threshold voltage is corrected to be lower (refer to patent document 1: Japanese Patent Application Laid-Open No. Hei. 9-130232).
Further, as shown in FIG. 13, integrated circuit body 16B, monitor section 15B monitoring drain current of at least one of a plurality of NchMOS transistors, and substrate voltage regulating section 14B controlling substrate voltage BN of a semiconductor substrate in such a manner that drain current becomes fixed are provided on the semiconductor substrate. The drain of NchMOS transistor 11B is connected to constant current source 12B, the source is connected to earth potential VSS terminal, the gate is set to an arbitrary voltage 17B, and the voltage of reference input IN1 of comparator 13B is set to a power supply voltage value. Input IN2 that is the subject of measurement side of comparator 13B is connected to the drain of the MOS transistor 11B (refer to patent document 2: Japanese Patent Application Laid-Open No. 2004-165649).
Further, in patent document 2, as shown in FIG. 14, integrated circuit body 16A, monitor section 15A monitoring drain current of at least one of a plurality of PchMOS transistors, and substrate voltage regulating section 14A controlling reference voltage BP of a semiconductor substrate are provided on the semiconductor substrate. The monitor section is comprised of a constant current source 12A, and a comparator section 13A comparing source potential of a PchMOS transistor for monitor use and a reference potential determined in advance in a state where a drain of PchMOS transistor 11A for monitor use formed on the same substrate as the plurality of PchMOS transistors and drains of a plurality of PchMOS transistors or NchMOS transistors of the integrated circuit body are connected to a terminal of earth potential VSS terminal. Results of the comparison are then fed-back to the substrate voltage of the PchMOS transistor for monitor use.
Further, as shown in FIG. 15, a monitor section monitoring drain potential of an NchMOS transistor where a gate and drain are connected to a constant current source and a substrate voltage regulating section controlling substrate voltage Vbn of a semiconductor substrate in such a manner that substrate potential becomes constant are provided. The drain of the NchMOS transistor is then connected to one side of the comparator, and the other is connected to reference potential Vgsn (constant potential). Output of the comparator is then inputted to the substrate voltage regulating section and a reference voltage Vbn is generated from the substrate voltage regulating section. Refer, for example, to (Sumita, M. et al., “Mixed Body Bias Techniques With Fixed Vt and Ids Generation Circuits” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005).
However, semiconductor integrated circuit apparatus of the related art have the following three problems. A first problem is that, in the methods of patent document 1 and patent document 2, as these are both methods for detecting fluctuation of drain potential of a leakage current detection NchMOS transistor, if there is no drain potential fluctuation from an initial potential to a potential exceeding a reference potential for detecting fluctuation of drain potential, it is not possible to detect change in leakage current. This also limits detection sensitivity for leakage current detection and improvement of response.
Further, in a second problem, with the PchMOS transistor substrate voltage control disclosed in patent document 2, restrictions exist in connecting a drain of a PchMOSFET for monitor use and drains of a plurality of PchMOSFETs or NchMOSFETs of an integrated circuit body to an earth potential VSS terminal. This results in the drawback of limitations such as circuit connection limitations being placed on the circuit design.
Further, in a third problem with the method of patent document 2 and patent document 3, because a comparator employing a comparator or operation amplifier is used, a DC offset error of the comparator becomes a threshold voltage setting value error.